1. Field of the Invention
The present invention relates to a contention priority control circuit, particularly, to a ring arbiter with two priority classes and, more particularly, to a contention priority control circuit applied, e.g., to realize an output cell select function in an ATM (Asynchronous Transfer Mode) switching.
2. Description of the Prior Art
General ATM switching architectures include an output buffer type architecture, shared buffer type architecture, input buffer type architecture, and cross-point type architecture.
For example, an output buffer type switch is advantageous because of high throughput and simple control. This output buffer type switch, however, multiplexes and buffers input ATM cells. This operation decreases the processing speed, and the input/output link speed is difficult to increase.
In recent years, high-speed, large-scale switches are being realized along with an abrupt increase in traffic for the Internet and an increase in ATM network speed using an optical fiber and like.
To follow this trend, the output buffer type switch realizes a large-scale switch by, e.g., connecting switches of the ATM switching serving as cores in a square matrix. This connection requires a function of copying an input cell with respect to horizontal core switches, and a function of selecting an output cell with respect to vertical core switches. A ring arbiter is applied to realize this output select function in the ATM switching.
In a recent ATM switching, a plurality of priority classes must be set in cell buffers to process cells within the switch based on the priority classes in order to ensure QOS (Quality Of Service). Further, switches must be multistage-connected to increase the switch scale.
However, a conventional ring arbiter returns only one output permission for output requests that are not discriminated by priority classes between ports.
No prior art realizes a ring arbiter which is constituted by multistage-connecting switches and arbitrates cell output contention between output ports when the ring arbiter has cell buffers for, e.g., two priority classes.
The present invention has been made to overcome the conventional drawbacks, and has as its object to provide a ring arbiter which is constituted by multistage-connecting switches, and arbitrates cell output contention between output ports when the ring arbiter has cell buffers for, e.g., two priority classes.
To achieve the above object, according to the first aspect of the present invention, there is provided a contention priority control circuit which receives data of two priority classes from a plurality of input ports, and arbitrates contention between output requests for outputting the plurality of data to a bus on the basis of the priority classes and priorities determined for the respective input ports.
According to the second aspect of the present invention, there is provided a circuit capable of arbitrating output requests between ports when a plurality of ports having data to be output onto a bus simultaneously exist on the bus connected to n (at least two) ports, and arbitrating contention of data output requests between ports and between priority classes when a contention priority control circuit for determining a port for outputting data to the bus receives high- and low-priority class data output requests at respective ports.
According to the third aspect of the present invention, there is provided an ATM switchboard comprising the contention priority control circuit defined in the first or second aspect.
As is apparent from the above aspects, the present invention can arbitrate contention between ports and between two priority classes.
A conventional ring arbiter must search on a high-priority class side on a ring-like control line in the first cycle and search on a low-priority class side in the second cycle. To the contrary, the present invention adopts a forward high-priority ring, forward low-priority ring, and backward high-priority ring. Search is done on respective ring control lines in parallel with each other, thereby reducing the processing time to one cycle at maximum. The processing time can be shortened.
The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principle of the present invention are shown by way of illustrative examples.